1. Field of the Invention
The present invention relates to a decoding device which is used in a full-duplex-type modem (i.e., a modulator-demodulator utilizing a full-duplex data transmission).
2. Related Art
Conventionally, the full-duplex-type modems employ a known encoding-decoding method utilizing a combination of a convolution-encoding device and a quadrature amplitude-phase modulator. As the convolution-encoding device, a trellis encoder is known. Hereinafter, the operations of the above-mentioned encoding-decoding method will be described by referring to V.32 bis standard from the recommendations of the CCITT (i.e., Comite Consultatif Internationale de Telegraphique et Telephonique; an international body that develops communications standards).
According to this method, serial data to be transferred at speed of 14400 Bps (where "Bps" represents a unit called bits per second) are divided into a plurality of unit data each consisting of six bits. Each 6-bit data within those unit data is converted into 7-bit data by the encoding operation performed by the trellis encoder. At a certain sampling moment "n", certain 6-bit data consisting of six bits called Q6n, Q5n . . . , Q1n is converted into certain 7-bit data consisting of seven bits called Y6n, Y5n . . . , Y0n, for example. In this case, the trellis encoder directly uses high-order four bits Q6n to Q3n in the 6-bit data as high-order four bits Y6n to Y3n in the 7-bit data to be outputted. On the other hand, low-order two bits Q2n and Q1n are supplied to a differential encoder, from which two bits Y2n and Y1n are obtained. Based on those bits Y2n and Y1n, the trellis encoder determines a least significant bit Y0n in accordance with a certain state transition rule as shown in FIG. 13. This bit Y0n is added to the six bits Y6n to Y1n as a redundant bit.
Then, the 7-bit data consisting of the bits Y6n to Y0n are subjected to quadrature amplitude modulation called "QAM". FIG. 14 shows a signal space diagram having signal-placing points each indicative of each of digital signals in an amplitude-phase plane before performing the modulation.
In a receiving modem, signals transmitted from a sending modem are subjected to QAM decoding, thus obtaining coordinate information (Xnr, Ynr), regarding a receiving point, on the amplitude-phase plane. The coordinate information is supplied to a decoding system as shown in FIG. 15. At first, an area comparison portion 1 performs an area comparison based on the coordinates Xnr, Ynr on the amplitude-phase plane. This example uses eight kinds of area comparisons as shown in FIGS. 16(A) to 16(D) and FIGS. 17(A) to 17(D) so as to obtain a candidate path for each of eight sets of low-order three bits Y2n, Y1n and Y0n: (000), (001) . . . , (111). A candidate-path-coordinate determining portion 2 shown in FIG. 15 determines eight sets of coordinates for the candidate paths. Then, a distance computing portion 3 computes a distance between a point defined by the coordinates of each candidate path and another point defined by the coordinates Xnr, Ynr. In accordance with the state transition rule as shown In FIG. 13, a viterbi decoder 4 works to select one of the candidate paths as a surviving path which has the smallest sum of the distances between the points. For example, in order to obtain the surviving path with respect to twelve stages (or twelve sampling periods), the viterbi decoder 4 firstly chooses the paths each of which can lead a searching route from each of states, denoted by "S000", "S001", . . . , "S111" shown in FIG. 13, to a desired state after passing through twelve stages; and then, the viterbi decoder 4 finally selects the shortest path among the chosen paths. At a time when the surviving path is obtained, previous receiving data, which has been supplied at a previous timing which is the twelve sampling moments before the current sampling moment, is defined.
In the conventional decoding device as described above, when one receiving point is given, the area comparisons as shown in FIGS. 16(A) to 17(D) should be performed plural times so as to determine a plurality of candidate paths. In other words, the conventional decoding device requires complicated area-comparison/judgement processes, which raises a drawback that a relatively long time should be required.
Moreover, when performing the viterbi decoding, the high-order four bits to be coupled with the low-order three bits must be stored with respect to each of the states. Further, those data required for each state should be memorized with respect to each of twelve stages If the twelve stages are required for determining the surviving path. In such case, a random-access memory (i.e., RAM) 5 must store a large amount of data, the number of which corresponds to 4 (bits).times.8 (states).times.12 (stages). This requires a large storage capacity for the RAM 5.